Contents
Compuertas
Compuerta AND de dos entradas
- Descarge este codigo [direccion_de_descarga aquí verilog/and/and2in_tb.v]
- Descarge el vcd de este codigo [direccion_de_descarga aquí verilog/and/and2in_tb.vcd]
Nota:este codigo ya se probó así:
compilación con icarus verilog
simulación del vcd con gtkwave
1 module and2in (/*AUTOARG*/
2 // Outputs
3 out,
4 // Inputs
5 in1, in2
6 ) ;
7 output out;
8 input in1, in2;
9 and (out, in1, in2 );
10 endmodule // and2in
11
12 module and2in_tb (/*AUTOARG*/) ;
13 /*AUTOWIRE*/
14 // Beginning of automatic wires (for undeclared instantiated-module outputs)
15 wire out; // From ag of and2in.v
16 // End of automatics
17 /*AUTOREG*/
18 // Beginning of automatic regs (for this module's undeclared outputs)
19 // End of automatics
20 /*AUTOREGINPUT*/
21 // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
22 reg in1; // To ag of and2in.v
23 reg in2; // To ag of and2in.v
24 // End of automatics
25 and2in ag (/*AUTOINST*/
26 // Outputs
27 .out (out),
28 // Inputs
29 .in1 (in1),
30 .in2 (in2));
31 `timescale 1s/100ps
32 initial begin
33 in1=0;
34 in2=0;
35 end
36 always
37 #1 in1=!in1;
38 always
39 #2 in2=!in2;
40 initial begin
41 $dumpfile ("and2in_tb.vcd");
42 $dumpvars;
43 end
44 initial
45 #17 $finish;
46 endmodule // and2in_tb
Compuerta OR de dos entradas
- Descarge este codigo [direccion_de_descarga aquí verilog/or/or2in_tb.v]
- Descarge el vcd de este codigo [direccion_de_descarga aquí verilog/or/or2in_tb.vcd]
Nota:este codigo ya se probó así:
compilación con icarus verilog
simulación del vcd con gtkwave
1 module or2in (/*AUTOARG*/
2 // Outputs
3 out,
4 // Inputs
5 in1, in2
6 ) ;
7 output out;
8 input in1, in2;
9 or (out, in1, in2 );
10 endmodule // or2in
11
12 module or2in_tb (/*AUTOARG*/) ;
13 /*AUTOWIRE*/
14 // Beginning of automatic wires (for undeclared instantiated-module outputs)
15 wire out; // From ag of or2in.v
16 // End of automatics
17 /*AUTOREG*/
18 // Beginning of automatic regs (for this module's undeclared outputs)
19 // End of automatics
20 /*AUTOREGINPUT*/
21 // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
22 reg in1; // To ag of or2in.v
23 reg in2; // To ag of or2in.v
24 // End of automatics
25 or2in ag (/*AUTOINST*/
26 // Outputs
27 .out (out),
28 // Inputs
29 .in1 (in1),
30 .in2 (in2));
31 initial begin
32 in1=0;
33 in2=0;
34 end
35 always
36 #1 in1=!in1;
37 always
38 #2 in2=!in2;
39 initial begin
40 $dumpfile ("or2in_tb.vcd");
41 $dumpvars;
42 end
43 initial
44 #5 $finish;
45 endmodule // or2in_tb
Compuerta NAND de dos entradas
- Descarge este codigo [direccion_de_descarga aquí verilog/nand/nand2in_tb.v]
- Descarge el vcd de este codigo [direccion_de_descarga aquí verilog/nand/nand2in_tb.vcd]
Nota:este codigo ya se probó así:
compilación con icarus verilog
simulación del vcd con gtkwave
1 module nand2in (/*AUTOARG*/
2 // Outputs
3 out,
4 // Inputs
5 in1, in2
6 ) ;
7 output out;
8 input in1, in2;
9 nand (out, in1, in2 );
10 endmodule // nand2in
11
12 module nand2in_tb (/*AUTOARG*/) ;
13 /*AUTOWIRE*/
14 // Beginning of automatic wires (for undeclared instantiated-module outputs)
15 wire out; // From ag of nand2in.v
16 // End of automatics
17 /*AUTOREG*/
18 // Beginning of automatic regs (for this module's undeclared outputs)
19 // End of automatics
20 /*AUTOREGINPUT*/
21 // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
22 reg in1; // To ag of nand2in.v
23 reg in2; // To ag of nand2in.v
24 // End of automatics
25 nand2in ag (/*AUTOINST*/
26 // Outputs
27 .out (out),
28 // Inputs
29 .in1 (in1),
30 .in2 (in2));
31 `timescale 1s/100ps
32 initial begin
33 in1=0;
34 in2=0;
35 end
36 always
37 #1 in1=!in1;
38 always
39 #2 in2=!in2;
40 initial begin
41 $dumpfile ("nand2in_tb.vcd");
42 $dumpvars;
43 end
44 initial
45 #5 $finish;
46 endmodule // nand2in_tb
Compuerta NOR de dos entradas
- Descarge este codigo [direccion_de_descarga aquí verilog/nor/nor2in_tb.v]
- Descarge el vcd de este codigo [direccion_de_descarga aquí verilog/nor/nor2in_tb.vcd]
Nota:este codigo ya se probó así:
compilación con icarus verilog
simulación del vcd con gtkwave
1 module nor2in (/*AUTOARG*/
2 // Outputs
3 out,
4 // Inputs
5 in1, in2
6 ) ;
7 output out;
8 input in1, in2;
9 nor (out, in1, in2 );
10 endmodule // nor2in
11
12 module nor2in_tb (/*AUTOARG*/) ;
13 /*AUTOWIRE*/
14 // Beginning of automatic wires (for undeclared instantiated-module outputs)
15 wire out; // From ag of nor2in.v
16 // End of automatics
17 /*AUTOREG*/
18 // Beginning of automatic regs (for this module's undeclared outputs)
19 // End of automatics
20 /*AUTOREGINPUT*/
21 // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
22 reg in1; // To ag of nor2in.v
23 reg in2; // To ag of nor2in.v
24 // End of automatics
25 nor2in ag (/*AUTOINST*/
26 // Outputs
27 .out (out),
28 // Inputs
29 .in1 (in1),
30 .in2 (in2));
31 initial begin
32 in1=0;
33 in2=0;
34 end
35 always
36 #1 in1=!in1;
37 always
38 #2 in2=!in2;
39 initial begin
40 $dumpfile ("nor2in_tb.vcd");
41 $dumpvars;
42 end
43 initial
44 #5 $finish;
45 endmodule // nor2in_tb
Compuerta XOR de dos entradas
- Descarge este codigo [direccion_de_descarga aquí verilog/xor/xor2in_tb.v]
- Descarge el vcd de este codigo [direccion_de_descarga aquí verilog/xor/xor2in_tb.vcd]
Nota:este codigo ya se probó así:
compilación con icarus verilog
simulación del vcd con gtkwave
1 module xor2in (/*AUTOARG*/
2 // Outputs
3 out,
4 // Inputs
5 in1, in2
6 ) ;
7 output out;
8 input in1, in2;
9 xor (out, in1, in2 );
10 endmodule // xor2in
11
12 module xor2in_tb (/*AUTOARG*/) ;
13 /*AUTOWIRE*/
14 // Beginning of automatic wires (for undeclared instantiated-module outputs)
15 wire out; // From ag of xor2in.v
16 // End of automatics
17 /*AUTOREG*/
18 // Beginning of automatic regs (for this module's undeclared outputs)
19 // End of automatics
20 /*AUTOREGINPUT*/
21 // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
22 reg in1; // To ag of xor2in.v
23 reg in2; // To ag of xor2in.v
24 // End of automatics
25 xor2in ag (/*AUTOINST*/
26 // Outputs
27 .out (out),
28 // Inputs
29 .in1 (in1),
30 .in2 (in2));
31 initial begin
32 in1=0;
33 in2=0;
34 end
35 always
36 #1 in1=!in1;
37 always
38 #2 in2=!in2;
39 initial begin
40 $dumpfile ("xor2in_tb.vcd");
41 $dumpvars;
42 end
43 initial
44 #5 $finish;
45 endmodule // xor2in_tb
Compuerta XNOR de dos entradas
- Descarge este codigo [direccion_de_descarga aquí verilog/xnor/xnor2in_tb.v]
- Descarge el vcd de este codigo [direccion_de_descarga aquí verilog/xnor/xnor2in_tb.vcd]
Nota:este codigo ya se probó así:
compilación con icarus verilog
simulación del vcd con gtkwave
1 module xnor2in (/*AUTOARG*/
2 // Outputs
3 out,
4 // Inputs
5 in1, in2
6 ) ;
7 output out;
8 input in1, in2;
9 xnor (out, in1, in2 );
10 endmodule // xnor2in
11
12 module xnor2in_tb (/*AUTOARG*/) ;
13 /*AUTOWIRE*/
14 // Beginning of automatic wires (for undeclared instantiated-module outputs)
15 wire out; // From ag of xnor2in.v
16 // End of automatics
17 /*AUTOREG*/
18 // Beginning of automatic regs (for this module's undeclared outputs)
19 // End of automatics
20 /*AUTOREGINPUT*/
21 // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
22 reg in1; // To ag of xnor2in.v
23 reg in2; // To ag of xnor2in.v
24 // End of automatics
25 xnor2in ag (/*AUTOINST*/
26 // Outputs
27 .out (out),
28 // Inputs
29 .in1 (in1),
30 .in2 (in2));
31 initial begin
32 in1=0;
33 in2=0;
34 end
35 always
36 #1 in1=!in1;
37 always
38 #2 in2=!in2;
39 initial begin
40 $dumpfile ("xnor2in_tb.vcd");
41 $dumpvars;
42 end
43 initial
44 #5 $finish;
45 endmodule // xnor2in_tb
Compuerta NOT
- Descarge este codigo [direccion_de_descarga aquíverilog/not/or2in_tb.v ]
- Descarge el vcd de este codigo [direccion_de_descarga aquí verilog/not/or2in_tb.vcd]
Nota:este codigo ya se probó así:
compilación con icarus verilog
simulación del vcd con gtkwave
1 module not2in (/*AUTOARG*/
2 // Outputs
3 out,
4 // Inputs
5 in1
6 ) ;
7 output out;
8 input in1;
9 not (out, in1 );
10 endmodule // not2in
11
12 module not2in_tb (/*AUTOARG*/) ;
13 /*AUTOWIRE*/
14 // Beginning of automatic wires (for undeclared instantiated-module o utputs)
15 wire out; // From ag of not2in.v
16 // End of automatics
17 /*AUTOREG*/
18 // Beginning of automatic regs (for this module's undeclared outputs)
19 // End of automatics
20 /*AUTOREGINPUT*/
21 // Beginning of automatic reg inputs (for undeclared instantiated-mod ule inputs)
22 reg in1; // To ag of not2in.v
23 // End of automatics
24 not2in ag (/*AUTOINST*/
25 // Outputs
26 .out (out),
27 // Inputs
28 .in1 (in1));
29 initial begin
30 in1=0;
31 end
32 always
33 #1 in1=!in1;
34 initial begin
35 $dumpfile ("not2in_tb.vcd");
36 $dumpvars;
37 end
38 initial
39 #5 $finish;
40 endmodule // noty2in_tb